The present invention relates to a semiconductor memory device for writing/erasing data into/from a memory cell transistor with tunneling current.
Data erasure of a NAND type flash memory is executed every block, that is, data erasure is executed on all memory cell transistors in a selected block concurrently. In other words, data erasure is never executed on all memory cell transistors of non-selected blocks (for example, see JP-A-7-169284).
Here, in an erasing operation of a NAND flash memory, a boosted erasure voltage (for example, about 20V) is applied to the well of a memory cell transistor, and further a voltage of 0V is applied to all word lines WL of a selected block.
On the other hand, all word lines WL of non-selected blocks are controlled to be under a floating state. Accordingly, When the erasure voltage (about 20V) is applied to the well, a voltage having the same level as the boosted erasure voltage (20V) is applied to all the word lines WL of the non-selected blocks due to coupling. Here, the word lines WL are connected to the drain side of MOS transistors of a row decoder. In the erasing operation, the MOS transistors connected to the word lines WL of the selected block are set to ON state, and the source voltage thereof is controlled to 0V. On the other hand, the MOS transistors connected to the word lines WL of the non-selected blocks are set to OFF state (the gate voltage is set to 0V) and the source voltage is controlled to 0V.
Accordingly, when the erasure voltage is applied to the well as described above, the MOS transistors connected to the word lines WL of the non-selected blocks are set to the state that 20V is applied to the drains thereof, 0V is applied to the gates thereof and 0V is applied to the sources thereof. When this state is continued, the cut-off characteristics of the MOS transistors concerned are deteriorated, and thus leak current increases. Accordingly, the potential of the word lines WL of the non-selected blocks are lowered during erasing operation. When the potential of the word lines WL of the non-selected blocks is lowered to some level, erroneous erasure occurs. That is, as the erasing time (the time for which the erasure voltage is continued to be applied to the well) is longer, the voltage drop of the word lines WL of the non-selected blocks is more intense, so that erroneous erasure occurs with higher probability.